As chip-multiprocessors (CMPs) are becoming the dominant vehicle for general-purpose processing, the issues of efficient evaluation, convenient program and quick debug are becoming more and more important. Our current research mainly focuses on simulation acceleration, software debug and programming model. Our research also involves different optimizing techniques, such as phase behavior analysis and dynamic scheduling etc.
- [Publication] November, 2012, Our Paper “Multi-level Phase Analysis for Sampling Simulation.” has been accepted by Design, Automation & Test in Europe Conference & Exhibition (DATE 2013).
- [Publication] May, 2012, Our Paper “Adaptive Pipeline Parallelism for Image Feature Extraction Algorithms.” has been accepted by The 41st International Conference on Parallel Processing (ICPP 2012).
- [Publication] April, 2012, Our Paper “Improving Dynamic Prediction Accuracy Through Multi-level Phase Analysis.” has been accepted by the 2012 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2012).
- [Publicacion] Feburary, 2012, Our Paper “Transformer: A Functional-Driven Cycle-Accurate Multicore Simulator.” has been accepted by 49th Design Automation Conference (DAC 2012).
- Feiwen Zhu, Software Engineer, Nvidia
- Yibin Hu, Software Engineer, National Instruments
- Xun Li, Ph.D Student, University of University of California, Santa Barbara
- Tao Bao, Ph.D Student, Purdue University
- Junpu Chen, Software Engineer, Microsoft
- Yao Zhang, Software Engineer, Morgan
- Qiang Yan, Ph.D Student, Singapore Management University
- Qin Wang, Software Engineer, Synopsys
- Jie Yan, Software Engineer, Synopsys
- Lili Liu, Software Engineer, Huawei
- Xiaoxi Yang, Assistant Professor, Chanzhou College of Information Technology
- Ying Yuan, Master Student, Carnegie Mellon University